Track-and-Hold (T/H) circuits are used in electrical engineering systems such as Analog-to-Digital Converters (ADC) to sample a time varying input signal. Two phases of a T/H circuit define its overall functionality; a track phase and a hold phase. Sampling the time varying input signal is done with a semiconductor switch and a sampling capacitor. A schematic representation of a simple T/H circuit is shown in FIG. 1.
In FIG. 1, an alternating current voltage source 10 is connected to a switch 12, generally referred to as a tracking switch, at node 11. The tracking switch is controlled by Clock signal 14 and connects the voltage source to a charge storage device, for example a capacitor 16 when the switch is turned on, defining the sampling instant. An output voltage is measured at node 18.
A track phase is defined when the Clock signal is logic level high (‘high’). In this phase, the tracking switch is closed and the output voltage tracks the voltage source 10. A hold phase is defined when the Clock signal is logic level low (‘low’) and a sample instance of the input voltage is taken. In the hold phase, switch 12 is open circuited.
During the track phase, a charge is placed on capacitor 16 corresponding to the voltage at node 11. When the track phase ends (i.e. as the hold phase begins) the capacitor 16 holds a charge directly proportional to the value of the voltage source 10 at the instant the tracking switch is turned off.
Tracking switch 12 in a T/H circuit is commonly a Metal Oxide Semiconductor (MOS) device. MOS configurations used in a T/H circuit are Complementary MOS (CMOS), N-channel MOS (NMOS) or P-channel MOS (PMOS).
FIG. 2 is a detailed schematic that illustrates a T/H circuit conceptualized in FIG. 1. Tracking switch 12 from FIG. 1 is replaced by an NMOS device 22 and is detailed with charge flow represented by directional arrows 24 and 26. When the Clock signal 14 is high, a channel charge forms in the device 22, providing a conduction path between the nodes 11 and 18. When the Clock signal 14 transitions from high to low, the channel charge must exit the device 22 as indicated by the arrows 24 and 26. This charge is subsequently referred to as ‘charge injection’.
When entering a hold phase (i.e. when the NMOS device 22 is open), a fraction of the total channel charge is injected towards the voltage source 10 as well as the capacitor 16 (indicated by reference numerals 24 and 26). A voltage step, or pedestal, at node 18 is created as a result of a residual channel charge 26 being injected towards node 18.
The T/H circuit shown in FIG. 1 and FIG. 2 is not ideal and exhibits significant performance issues. Various sources of errors are attributed to it; notably, the charge injected from the channel of NMOS switch 22 that induces a pedestal error at node 18 during the hold phase.
FIG. 3 is a schematic diagram that illustrates a solution in the art employed to overcome the problem of the charge injection towards the output voltage (reference numeral 26 in FIG. 2). Similar in design to the circuit shown in FIG. 2, it consists of an additional device, shown in FIG. 3 as an NMOS device 30, connected to the output of tracking switch 22. The NMOS device 30 has its drain and source nodes shorted together to allow node 18 to track the input voltage source (during the track phase). The control terminal of NMOS device 30 is connected to Second Clock 32, which is out of phase with Clock signal 14.
During the transition from the track phase to the hold phase, the NMOS device 22 injects channel charge 26 towards NMOS device 30. Soon after, triggered by the Second Clock 32 signal that is out of phase with the Clock 14 signal, a channel is also formed in the device 30. The goal in the prior art implementation of FIG. 3 is to choose the right size (channel area) of device 30, such that the charge required to form device 30's channel is precisely the same as charge 26. If device 30 is sized correctly, there will not be any residual pedestal at node 18.
However, this prior art is difficult to implement in practice during the design phase as finding the correct size of the compensation device is a non-trivial and error-prone exercise. As such, the prior art is inappropriate for low cost precision ADC systems where circuitry connected to node 18 can respond nonlinearly to a pedestal error. This can be a particular problem in low voltage IC processes. The nonlinear circuit response can manifest itself as harmonic distortion or intermodulation distortion of the signal.
FIG. 4 is a schematic diagram that illustrates another solution in the art by incorporating a bottom-plate sampling sub-circuit. The T/H circuit in FIG. 4 is an improvement over that shown in FIG. 3 and has an additional NMOS switch 44 connected to the bottom-plate of capacitor 16. The control terminal of switch 44 is connected to Sample signal 42.
In the circuit described above, Sample 42 is brought to logic level low (prior to Clock 14 going to logic level low). This open-circuits the bottom-plate of capacitor 16, defining the sampling instant for this T/H circuit design. With the bottom-plate open-circuited, the charge stored on the capacitor remains constant, regardless of the voltage fluctuation on the output voltage node 18. With Sample held low, Clock 14 is then brought low (hold phase). Uncompensated channel charge 24 and 26 is distributed between the input node 11 and the output voltage node 18. Open circuiting the bottom-plate of capacitor 16 prevents the injected charge 26 from altering the charge stored on capacitor 16.
The Sample signal 42 is brought high (while Clock 14 is still low) to set a common-mode voltage reference for the capacitor's bottom-plate, thereby establishing a ground reference at node 18.
However, a parasitic capacitance 46 (of switch 44) prevents the bottom-plate of capacitor 16 from being completely isolated from the ground node. Capacitors 16 and 46 form a capacitive voltage divider, which allows a portion of the voltage pedestal at node 18 to be applied to capacitor 16, altering the sample charge stored on capacitor 16. Some of the uncompensated channel charge ejected from the tracking switch will find its way onto capacitor 16, introducing a signal dependent non-linearity.
FIG. 5A describes another solution in the art by incorporating a bootstrap circuit into the T/H. The circuit shown in FIG. 5 is similar to that in FIG. 2 with an additional voltage source 60 added between the control terminal of the tracking switch 22 and Clock line 14.
Bootstrapped T/H circuits arrange for the drive voltage on tracking switch 22 to track the input voltage source 10. This results in a gate-source voltage on the tracking switch that is constant from sample to sample. This serves to improve the linearity of the tracking switch. Inadequate compensation for the injected charge 26 in the circuit of FIG. 5A can result in a large pedestal error. In modern low-voltage circuit processes, this pedestal can often be large enough to shift the common-mode voltage range at node 18 outside of the valid operating range for circuitry that follows the T/H.
This limitation can be addressed with the addition of a charge compensation device 30 in FIG. 5B. The channel area of device 30 is selected to ensure that the magnitude of compensation charge 28 is sufficient to shift the output common-mode voltage into an optimal range for the circuitry that follows a bootstrapped T/H sub-circuit.
The prior art solutions shown above in FIGS. 3, 4 and 5B all require the compensation charge 28 to be precisely related to injected charge 26. The prior art solutions seldom achieve optimal performance, because determining the amount of uncompensated channel charge injected towards the output node is a complex function of parameters such as the relative impedance of the input voltage source and capacitance and the fall time of the Clock 14. To further compound the problem, circuit simulators neither model nor predict the charge injection phenomena with sufficient accuracy to reliably quantify the voltage pedestal prior to circuit fabrication.
Accordingly, there is a need for an improved way to accurately control the amount of charge compensation 28, and mitigate the expense and difficulty associated with finding the correct channel size of the charge compensation device.